ASIC Engineering Technical Leader (Design)

Cisco Systems, Inc.
United States, California, San Jose
170 W Tasman Dr (Show on map)
May 28, 2025
The application window is expected to close on 6/30/25. This role will be based onsite out of our San Jose, CA office. The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Meet the Team Our group offers a unique combination of a startup culture with the benefits of working for the leading networking company in the world. You will engage in dynamic collaboration with Senior micro-architects, designers, verification engineers and interact with cross-functional software and product teams, working together to ensure the successful deployment of the ASIC in products. Your Impact Development of high-performance designs/ASICs from specification to tape-out. Micro-architectural definition, writing micro-architecture and implementation specifications. Implement Verilog RTL to meet timing and performance requirements. Help define, evolve, and support our design methodology. Collaborate with the verification, PD, DFT, Package and SW teams to develop next generation ASICs. Perform diagnostic and post silicon validation tests in the lab. Work with hardware and software teams to triage and root cause system, software, and customer failures. Minimum Qualifications: Bachelor's degree in Electrical or Computer engineering and 8+ years of ASIC Design experience. Experience with Verilog and System Verilog programming. Experience in architecture and micro architecture development. Experience delivering ASIC designs from specification to tape-out. Preferred Qualifications: Master's degree in Electrical or Computer engineering and 6+ years of ASIC Design experience. Proven experience meeting and delivering project milestones and deadlines. Ability to communicate technical concepts to audiences spanning executives to junior engineers. Demonstrated ability in troubleshooting and debugging. Scripting experience (Python, Perl, TCL, shell programming). Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.