New

Principal Validation Engineer

Marvell Semiconductor, Inc.
paid time off, flex time, 401(k)
United States, California, Santa Clara
5488 Marvell Lane (Show on map)
Jun 06, 2025
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Marvell post silicon validation group designs and develops test platforms for validating IP's like PCIe, CXL, Ethernet, DDR etc. on custom silicon products used in communication infrastructure applications such as 5G base stations, AI infrastructure, Storage and cloud computing platforms. What You Can Expect Lab-based silicon bring-up and unit test execution focused on PCIe Physical and PCS layer hardware and firmware functionality, while also extending to the protocol layer of the PCIe or CXL stack. Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER. Troubleshoot failing tests with diagnostics, software tools, hardware analyzers, oscilloscopes, meters, logic/protocol analyzers. Leading collaborative technical discussions to drive resolution on technical issues Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to PCIe PHY. Work closely with customers to address design issue and debug failure cases What We're Looking For Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience. We are looking for hardware validation/applications engineer with experience in: PCIe and CXL protocol, architecture and electrical standards PCIe clocking architecture, reset schemes, power management, speed change, and equalization PCIe subsystem (PHY + MAC) and PIPE interface PCIe and CXL silicon bring-up, validation, and debug using exercisers and analyzers PCIe characterization and compliance test using standard lab equipment PCIe and CXL system interoperability Experience in system bring-up, validation, and debug with root-cause analysis Experience developing FW code (C programming) for system bring-up, validation, and debug Experience using standard lab equipment, including logic analyzers and oscilloscopes Experience writing scripts (Python or others) for silicon test and lab automation Expected Base Pay Range (USD) 143,200 - 214,500, $ per annum The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. #LI-TT1