Principal Analog Design Engineer

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

Seeking a Mixed Signal designer to be part of a key team designing highly sophisticated CMOS transceiver/SERDES products. Responsibilities would span architectural investigations and implementation for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs etc. to meet key performance targets and performing design verification using industry standard tools such as SPICE, Spectre, MATLAB etc.

As a Principal Analog circuit design engineer, you will be collaborating with system architects and a global team of circuit and physical designers to build best in class serial links for various applications and space. Your work would swing between research and development geared towards circuits at bleeding edge of technology and data rates to hands-on ('roll-up-the sleeve') design of key analog circuits.

What We're Looking For

• Completed a MS or PhD in Electrical Engineering with 5-10 years of related experience.
• Expertise in one or more of the following focus areas of analog design: ADC/DACs, Front-Ends, CTLE, PLL, Timing circuits, CDRs, SerDes.
• Ability to collaborate with various other design and functional teams: Layout/ Physical design, System architecture, Digital design and Validation for the successful development, release and support of complex mixed signal IPs
• Strong knowledge on the deep sub-micron CMOS technologies. Keen eye for analog layout in latest deep submicron technologies and supervision of the same to get the key performance for high-speed design
• Excellent problem solving and analytical skills to take on circuit design challenges.
• Excellent debug skills to drive test plans and support validation for full cycle development of IPs and products

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.